1. Field of the Invention
This invention relates to processors. More specifically, this invention relates to processors having an instruction decoder including an emulation ROM for emulating decoder logic.
2. Description of the Related Art
Advanced microprocessors, such as P6-class x86 processors, are defined by a common set of features. These features include a superscalar architecture and performance, decoding of multiple x86 instructions per cycle and conversion of the multiple x86 instructions into RISC-like operations. The RISC-like operations are executed out-of-order in a RISC-type core that is decoupled from decoding. These advanced microprocessors support large instruction windows for reordering instructions and for reordering memory references.
Performance of an advanced superscalar microprocessor is highly dependent upon decoding performance including decoding speed, the number of x86 instructions decoded in a single cycle, and branch prediction performance and handling. Instruction decoders in advanced superscalar microprocessors often include one or more decoding pathways in which x86 instructions are decoded by hardware logic translation and a separate decoding pathway which uses a ROM memory for fetching a RISC operation sequence that corresponds to an x86 instruction. Generally, x86 instructions that are translated by hardware logic are simple x86 instructions. The lookup ROM is used to decode more complex x86 instructions.
One problem with usage of a lookup ROM for decoding instructions is the overhead incurred in determining a ROM vector or entry point address and retrieving operations (Ops) from ROM. This overhead typically causes a penalty in decoder throughput for instructions that are decoded using the ROM. This throughput penalty lowers decoding performance.
A second problem with the usage of a lookup ROM for decoding x86 instructions is the existence of a large number of different CISC-tpe instructions that are standard for an x86 processor. Since a substantial number of instructions are implemented, a large ROM circuit on the processor chip is necessary.
Furthermore, the lookup ROM typically has only a few defmed entry points and the various x86 instructions translate to Op sequences in ROM having varying numbers of constituent Ops so that the sequences do not fit precisely between entry points without leaving distributed unused ROM locations. The existence of unused lookup ROM locations further expands the large size of the lookup ROM, increasing the size of the processor integrated circuit and thereby reducing manufacturing yields of the circuits and increasing production costs.
What is needed is a reduced-size and reduced-complexity ROM-based decoder in a superscalar instruction decoder.